Operations of Control Unit in different ways

Micro-Operation

The execution of a program consists of the sequential execution of instructions. Each instruction is executed during an instruction cycle made up of shorter sub-cycles (e.g., fetch, indirect, execute, interrupt). The performance of each sub-cycle involves one or more shorter operations, that is, micro-operations.

Micro-operations are the functional, or atomic, operations of a processor. In this section, we will examine micro-operations to gain an understanding of how the events of any instruction cycle can be described as a sequence of such micro-operations.

 

Four registers are involved in an Instruction Cycle:

·         Memory address register (MAR): Is connected to the address lines of the system bus. It specifies the address in memory for a read or write operation.

·         Memory buffer register (MBR): Is connected to the data lines of the system bus. It contains the value to be stored in memory or the last value read from memory.

·         Program counter (PC): Holds the address of the next instruction to be fetched.

·         Instruction register (IR): Holds the last instruction fetched.

The simple fetch cycle actually consists of three steps and four micro-operations. Each micro-operation involves the movement of data into or out of a register. So long as these movements do not interfere with one another, several of them can take place during one step, saving lime. Symbolically, we can write this sequence of events as follows:

t1: MAR <= (PC)

t2: MBR <= Memory

PC <= (PC) + l

t3: IR <= (MBR)

The Indirect Cycle

Once an instruction is fetched, the next step is to fetch source operands. Continuing our simple example, let us assume a one-address instruction format, with direct and indirect addressing allowed. If the instruction specifies an indirect address, then an indirect cycle must precede the execute cycle. The data flow includes the following micro-operations:

t1: MAR <= (IR (Address))

t2: MBR <= Memory

t3: IR(Address) <= (MBR(Address) )

The address field of the instruction is transferred to the MAR. This is then used to fetch the address of the operand. Finally, the address field of the IR is updated from the MBR, so that it now contains a direct rather than an indirect address.

The IR is now in the same state as if indirect addressing had not been used, and it is ready for the execute cycle. We skip that cycle for a moment, to consider the interrupt cycle.

The Interrupt Cycle

At the completion of the execute cycle, a test is made to determine whether any enabled interrupts have occurred. If so, the interrupt cycle occurs. The nature of this cycle varies greatly from one machine to another. We present a very simple sequence of events, we have

t1 : MBR <= (PC)

t2 : MAR <= Save_Address

PC <= Routine_Address

t3: Memory <= (MBR)

In the first step, the contents of the PC are transferred to the MBR, so that they can be saved for return from the interrupt. Then the MAR is loaded with the address at which the contents of the PC are to be saved, and the PC is loaded with the address of the start of the interrupt-processing routine. These two actions may each be a single micro-operation. However, because most processors provide multiple types and/or levels of interrupts, it may lake one or more additional micro-operations to obtain the save_address and the routine_address before they can be transferred to the MAR and PC, respectively. In any case, once this is done, the final step is to store the MBR, which contains the old value of the PC, into memory. The processor is now ready to begin the next instruction cycle.

Execute Cycle

Execute Cycle (ADD)

Different for each instruction

e.g. ADD R1,X - add the contents of location X to Register 1 , result in R1

t1:     MAR <- (IR address)

t2:     MBR <- (memory)

t3:     R1 <- R1 + (MBR)

NOTE: no overlap of micro-operations

Execute Cycle (ISZ)

ISZ X - increment and skip if zero

t1:     MAR <- (IR address)

t2:     MBR <- (memory)

t3:     MBR <- (MBR) + 1

t4:     memory <- (MBR)

                              if (MBR) == 0 then PC <- (PC) + 1

NOTES:

if is a single micro-operation

Micro-operations done during t4

Execute Cycle (BSA)

BSA X - Branch and save address

Address of instruction ff. BSA is saved in X

Execution continues from X+1

t1:     MAR <- (IR address)

                    MBR <- (PC)

t2:     PC <- (IR address)

                    memory <- (MBR)

t3:     PC <- (PC) + 1

The Instruction Cycle

We have seen that each phase of the instruction cycle can be decomposed into a sequence of elementary micro-operations. In our example, there is one sequence each for the fetch, indirect, and interrupt cycles, and, for the execute cycle, there is one sequence of micro-operations for each opcode.

We assume a new 2-bit register called the instruction cycle code (ICC). The ICC designates the state of the processor in terms of which portion of the cycle it is in:

00: Fetch

01: Indirect

10: Execute

11: Interrupt

At the end of each of the four cycles, the ICC is set appropriately. The indirect cycle is always followed by the execute cycle. The interrupt cycle is always followed by the fetch cycle. For both the execute and fetch cycles, the next cycle depends on the state of the system.

It defines the complete sequence of micro-operations, depending only on the instruction sequence and the interrupt pattern. Of course, this is a simplified example. In any case, we have reached the point in our discussion in which the operation of the processor is defined as the performance of a sequence of micro-operations. We can now consider how the control unit causes this sequence to occur.

 

Control Of The Processor

Functional requirement

With the information at hand, the following three-step process leads to a characterization of the control unit:

.       Define the basic elements of the processor.

.       Describe the micro-operations that the processor performs.

.       Determine the functions that the control unit must perform to cause the micro-operations to be performed.

We have already performed steps 1 and 2. Let us summarize the results. First, the basic functional elements of the processor are the following:

·         ALU

·         Registers

·         Internal data paths

·         External data paths

·         Control unit

The execution of a program consists of operations involving these processor elements. As we have seen, these operations consist of a sequence of micro-operations. All micro-operations fall into one of the following categories:

·         Transfer data from one register to another.

·         Transfer data from a register to an external interface (e.g., system bus).

·         Transfer data from an external interface lo a register.

·         Perform an arithmetic or logic operation, using registers for input and output.

We can now be somewhat more explicit about the way in which the control unit functions. The control unit performs two basic tasks:

·         Sequencing: The control unit causes the processor lo step through a series of micro-operations in the proper sequence, based on the program being executed.

·         Execution: The control unit causes each micro-operation to be performed.

Control Signals

We have defined the elements that make up the processor (ALU, registers, data paths) and the micro-operations that are performed. For the control unit to perform its function, it must have inputs that allow it to determine the slate of the system and outputs that allow it to control the behavior of the system. These are the external specifications of the control unit. Internally, the control unit must have the logic required lo perform its sequencing and execution functions.

The inputs are as follows:

·         Clock: This is how the control unit "keeps time." The control unit causes one micro-operation (or a set of simultaneous micro-operations) to be performed for each clock pulse. This is sometimes referred to as the processor cycle time. or the clock cycle lime.

·         Instruction register: The opcode of the current instruction is used lo determine which micro-operations lo perform during the execute cycle.

·         Flags: These are needed by the control unit to determine the status of the processor and the outcome of previous ALU operations. For example, for the increment-and-skip-if-zero (ISZ) instruction, the control until will increment the PC if the zero flag is set.

·         Control signals from control bus: The control bus portion of the system bus provides signals to the control unit, such as interrupt signals and acknowledgments.

The outputs are as follows:

·         Control signals within the processor: These are two types: those that cause data to be moved from one register to another, and those that activate specific ALU functions.

·         Control signals to control bus: These are also of two types: control signals lo memory, and control signals lo the I/O modules.

Internal Processor Organization

A single internal bus connects the ALU and all processor registers. Gates and control signals are provided for movement of data onto and off the bus from each register. Additional control signals control data transfer to and from the system (external) bus and the operation of the ALU.

Two new registers, labeled Y and Z have been added to the organization. These are needed for the proper operation of the ALU. When an operation involving two operands is performed, one can be obtained from the internal bus, but the other must be obtained from another source. The AC could be used for this purpose, but this limits the flexibility of the system and would not work with a processor with multiple general-purpose registers. Register Y provides temporary storage for the other input. The ALU is a combinatorial circuit with no internal storage, Thus, when control signals activate an ALU function, the input to the ALU is transformed to the output. Thus, the output of the ALU cannot be directly connected to the bus, because this output would feed back to the input. 

Control Unit

l  Two Control Unit

- Instruction decoder/machine cycle encoding

- Timing and Control

l  Essence is Timing and Control

- Inputs are in clock, current instructions and some control signals

- Outputs are control signals to processor and external bus

Hardwired Implementation

In a hardwired implementation, the control unit is essentially a state  machine circuit. Its input logic signals are transformed into a set of output logic signals, which are the control signals.

Control Unit Inputs

- Flags and control bus

Each bit means something

- Instruction register

Op-code causes different control signals for each different                             instruction

Unique logic for each op-code

Decoder takes encoded input and produces single output

- Clock

Repetitive sequence of pulses

Useful for measuring duration of micro-ops

Must be long enough to allow signal propagation

Different control signals at different times within instruction cycle

Need a counter with different control signals for t1, t2, etc.

Control Logic Unit

Each control signal, derive a boolean expression of signal as function of inputs. Consider logical view of control unit data paths.


Lets test your comprehension. Click Here!



References:

l  Stallings, W. Computer Organization and Architecture, 8th Edition. Upper Saddle River, Pearson Education, Inc., 2010.

l       FARH04 Farhat, H. Digital Design and Computer Organization. Boca Raton, FL: CRCPress, 2004.

l  MANO04 Mano, M. Logic and Computer Design Fundamentals. Upper Saddle River, NJ: Prentice Hall, 2004.